
Lesson 13 
Memory Organization & Addresses

		 A register is a small "unit" of memory. To build large memories, a large number of registers are grouped together on a single chip. The CPU then needs some means of identifying and accessing individual registers on a chip. This is referred to as memory organization, or addressing.
		 For detailed information, read the following section, THE GRAPHIC WINDOW, and refer to the illustration in the Graphic Window.
		 

THE GRAPHIC WINDOW

		 The Graphic Window depicts the scheme for addressing four 4-bit registers. On the right of the window are the four registers, shown in a column. A common data bus runs along the far right of the window, branching off to the four data inputs (D3-D0) at the top of each register, and the four data outputs (Q3-Q0) at the right side of each register. Click on the "Show Register" button to see a diagram of the exact wiring of a register to the data bus.
		 On the left side of the window are three Edit Boxes. The top box, labeled R/W', is the Read/Write control line. A value of "1" allows a memory read to take place, a value of "0" allows a memory write to take place.
		 The other two Edit Boxes (A1,A0) put values on the register address select lines. These two select lines determine which one of the four registers is to be accessed. These two lines run to a column of four AND gates. The configuration of the inverters connected to these AND gates give each gate its own "code", or address. Only a select line combination of 00 (A1=0,A0=0) will activate the top AND gate. The output of the top AND gate eventually reaches the top register. So the address of the top register is referred to as 00. Only a select line combination of 01 (A1=0,A0=1) will activate the 2nd from top AND gate, and the address of the 2nd from top register is then 01. Of the four AND gates in the column, ONLY ONE will ever have an output value of "1" at any given time. This permits only one register to be accessed at a time. 
		 Half way through the simulation the left side of the screen will clear and the connections of the clock (CLK) and the Read/Write line (R/W') will be shown. Then, either a memory write or a memory read takes place.

IMPORTANT:
		 Keep in mind that the configuration of the addressing lines makes it possible for only one register Input Enable (IE) or only one register Output Enable (OE) to have a value of "1" at any given time. This is what makes it possible for the registers to share a common data bus. After a memory read, the contents of only one register can be on the bus. During a memory write, only one register will have the contents of the data bus written to it.

		 The addressing system discussed here can easily be extended to much larger groups of memory registers. If there are n register select lines, they can access up to 2^n registers. So a system with 16 select lines can access 2^16 registers: 65,536 registers (64K of memory). 
		 For the system in the Graphic Window:

	# of select lines:  n = 2    
	# of registers:  2^n = 2^2 = 4

		 Enter a "1" or a "0" in each of the two address select line boxes (A1,A0) to choose which register is to be accessed. Enter a "1" in the R/W' box to read the contents of the register, enter a "0" to write to the register.

  A1  A0  R/W'                        result

   0   0   0        Write contents of data bus to top register
   0   0   1        Read contents of top register to the data bus  
   0   1   0        Write contents of data bus to 2nd from top register
   0   1   1        Read contents of 2nd from top register to the data bus  
   1   0   0        Write contents of data bus to 3rd from top register
   1   0   1        Read contents of 3rd from top register to the data bus  
   1   1   0        Write contents of data bus to bottom register
   1   1   1        Read contents of bottom register to the data bus  


Lesson 14 
MBR & MAR

		 Lesson 13 showed the system for addressing registers in memory. To access a register in main memory, the CPU sends out an address on the address lines that travel between the CPU and main memory. If a memory read is to take place, the CPU sends out a control signal such as a "1" on the R/W' line. The register in memory then releases its contents to the data bus. If a memory write is to take place, the CPU also puts the data to write on the data bus and sends a control signal, such as a "0" on the R/W' line. The process of accessing memory takes longer than one clock state. Because of this, the correct address and data values must be held someplace so that they do not get overwritten by any other values that may enter the common buses. Two registers, the Memory Address Register (MAR) and the Memory Buffer Register (MBR), serve this need. 
		 The MAR holds the address of the register that is to be accessed in main memory. The MBR holds the data that is to be written to memory or the data that was read from memory.


THE GRAPHIC WINDOW

		 The Graphic Window depicts the MAR and the MBR. Both registers lie between the CPU and main memory. In this example, each register is 4-bits in size. The signals that control the Input Enables (IE) of these registers (RD,MBR,MAR) originate at the CPU. Sets of tri-state buffers control the direction of "flow" across the buses. The signals that control these buffers (WR,RD,MBR) originate at the CPU. 
		 Click on either the "Read" or the "Write" button, then run the simulation to see how the MAR and the MBR are used in the course of performing a memory read and a memory write.



